1. Field of the Invention
This invention relates to bias voltage generation and regulation in an integrated circuit dynamic random access memory. In particular, the invention relates to the pumping of charge from the substrate of the integrated circuit in response to timing signals provided by sub-circuitry of the integrated circuit; and, to clamping and modulation circuitry provided for regulation of the generated bias voltage.
In the present generation of dynamic random access memories (RAM's), it is desirable to generate voltages within the integrated circuit itself (i.e., "on-chip" voltage generator), rather than using an external-power supply. This eliminates the need for an additional external pin connector to the RAM integrated circuit. Furthermore, advanced technologies that allow for larger scale integration of memory circuits typically have higher resistivity substrates, more narrow transistor gates and thinner oxide layers. However, in order to minimize junction capacitances as well as threshold sensitivity to the drain voltage when using high resistivity substrates, it is desirable to reverse bias the substrate of the integrated circuit. The most important advantage of reverse-bias is the much reduced probability of localized forward biasing of junctions, which forward biasing injects electrons into the substrate and can lead to a malfunction of the RAM circuits or even seriously reduce refresh times. Another advantage of reverse-biasing of the substrate is an improvement in the speed and power of operation of the RAM. Reverse biasing as used herein refers to the application of a negative voltage to the device substrate wherein such device is fabricated as n-channel MOS. A positive reverse bias would be used for p-channel MOS, and a combination of the two used for CMOS devices. 2. Description of the Prior Art
The structure and operation of substrate bias generators for dynamic RAM's is taught elsewhere, for example, in papers by W. L. Martino, Jr., J. D. Moench, A. R. Bormann, and R. C. Tesch entitled "An On-Chip Back-Bias Generator for MOS Dynamic Memory," published in IEEE Journal of Solid-State Circuits, Vol. SC-15, No. 5, October, 1980, pp. 820-825; by J. M. Lee, J. R. Breivogel, R. Kunita and C. Webb entitled "A 80 ns 5 V-Only Kynamic RAM," published in the February 1979 proceedings of the IEEE International Solid-State Circuits Conference, pp. 142-143; by I. Itoh, R. Hori, H. Masuda and Y. Kamigaki entitled "A Single 5 V 64K Dynamic RAM" published in the February 1980 proceedings of the IEEE Solid-State Circuits Conference, pp. 228-229.